The present invention relates to a semiconductor memory device, a method for controlling a semiconductor memory device and a method for testing a semiconductor memory device. More particularly, this invention relates to a semiconductor memory device which executes an internal access operation and an external access operation.
Recently, semiconductor memory devices (dynamic random access memories (DRAMs)) with a large memory capacity have been used in electronic information devices. A DRAM has a self-refresh capability to refresh cell data of memory cells in accordance with a counter operation in an internal circuit. Because a DRAM with a self-refresh capability does not require an external refresh operation, it has advantages in that its power consumption is reduced and that the circuit design around the DRAM can be simplified.
A DRAM with a self-refresh capability may have contention between an internal refresh request (internal access) for retaining data and an external access request (external access) for writing or reading data. In a case where the internal access has priority, the external access is carried out after the internal access is finished. This case therefore requires about twice the time the access time needed in a case where the external access does not contend with the internal access. Therefore, there are demands for shortening the access time in a case where the external access does not contend with the internal access.
FIG. 1 is a schematic block circuit diagram of a control circuit 61 for a semiconductor memory device (DRAM) 60 which has the conventional self-refresh capability.
The control circuit 61 includes a command detector 62, an internal command generator 63, a refresh decision circuit 64 and a timing generator 65. The internal command generator 63 and the refresh decision circuit 64 constitute a so-called arbiter.
The command detector 62 decodes various commands, such as a write command and a read command, supplied from an external unit, and generates a command detection signal corresponding to the decoded command. In the example shown in FIG. 1, the command detector 62 detects a read command rdb and generates a read-command detection signal rd-cmd.
The refresh decision circuit 64 receives the read-command detection signal rd-cmd and a refresh request signal ref-req from an internal refresh timer (not shown), and determines which operation, the read operation or the refresh operation, has priority in accordance with the signals (rd-cmd and ref-req).
In a case where the refresh request signal ref-req is supplied at an earlier timing than the read-command detection signal rd-cmd, the refresh decision circuit 64 gives priority to the refresh operation. Specifically, the refresh decision circuit 64 generates a refresh start signal ref-start and a refresh state signal ref-state in response to the refresh request signal ref-req.
In a case where the read-command detection signal rd-cmd is supplied at an earlier timing than the refresh request signal ref-req, on the other hand, the refresh decision circuit 64 gives priority to the read operation. Specifically, the refresh decision circuit 64 generates the refresh start signal ref-start and the refresh state signal ref-state after a read state signal rd-state output from the timing generator 65 is reset (after the read operation is completed).
The internal command generator 63 generates a read start signal rd-start in accordance with the read-command detection signal rd-cmd from the command detector 62. At that time, in a case where the refresh operation has priority, the internal command generator 63 generates the read start signal rd-start after the refresh state signal ref-state is reset (after the refresh operation is completed).
In a case where the refresh operation has priority, the timing generator 65 generates a word-line enable timing signal wl-timing for enabling a word line corresponding to a predetermined refresh address in accordance with the refresh start signal ref-start.
In a case where the read operation has priority, on the other hand, the timing generator 65 generates the read state signal rd-state and the word-line enable timing signal wl-timing for enabling a word line in response to the read start signal rd-start. The word line to be enabled corresponds to a predetermined address which is given by an external address signal (not shown).
The operation of the DRAM 60 will be discussed next. FIG. 2 is an operational waveform diagram in a case where priority is given to an external access (read operation in this example) when the external access and an internal access (refresh operation) contend with each other.
Upon detection of the falling of a control signal supplied from an external unit, the command detector 62 decodes the read command rdb and generates the read-command detection signal rd-cmd. The read-command detection signal rd-cmd is supplied to the refresh decision circuit 64 at an earlier timing than the refresh request signal ref-req. At this time, the refresh decision circuit 64 gives priority to the read operation. The timing generator 65 generates the read state signal rd-state and the word-line enable timing signal wl-timing in accordance with the read start signal rd-start from the internal command generator 63. Cell data corresponding to a predetermined address is read out in accordance with the signal wl-timing.
After data reading is completed, the refresh decision circuit 64 generates the refresh start signal ref-start and the refresh state signal ref-state in accordance with the falling of the read state signal rd-state. In accordance with the refresh start signal ref-start, the timing generator 65 generates the word-line enable timing signal wl-timing. In accordance with the signal wl-timing, the refresh operation of a memory cell corresponding to a predetermined refresh address is carried out.
In a case where the external access (read operation) is given priority in the control circuit 61 with the arbiter capability, the refresh operation is executed after the read operation is completed.
FIG. 3 is an operational waveform diagram in a case where priority is given to an internal access when an external access and the internal access contend with each other. FIG. 3 shows a case where an external access time t8 or a time from the supply of the read command rdb to the DRAM 60 to the output of read data DQ from the DRAM 60 is longest (worst case).
Upon detection of the falling of a control signal supplied from an external unit, the command detector 62 decodes the read command rdb and generates the read-command detection signal rd-cmd. The refresh request signal ref-req is supplied to the refresh decision circuit 64 at an earlier timing than the read-command detection signal rd-cmd. At this time, the refresh decision circuit 64 gives priority to the refresh operation and generates the refresh start signal ref-start and the refresh state signal ref-state. The timing generator 65 generates the word-line enable timing signal wl-timing in accordance with the refresh start signal ref-start. The refresh operation of a memory cell corresponding to a predetermined refresh address is carried out in accordance with the signal wl-timing.
After the refresh operation is completed, the internal command generator 63 generates the read start signal rd-start in accordance with the falling of the refresh state signal ref-state. In accordance with the signal rd-start, the timing generator 65 generates the read state signal rd-state and the word-line enable timing signal wl-timing. In accordance with the signal wl-timing, cell data corresponding to a predetermined address is read out.
In a case where the internal access (refresh operation) is given priority in the control circuit 61, the read operation is executed after the refresh operation is completed.
In a case where the refresh operation is given priority (FIG. 3), however, an access delay occurs in the external access because the read operation is executed after the refresh operation is completed. In this case, the external access time t8 becomes the sum of the time needed for the normal read operation and the time needed for the refresh operation. Therefore, the external access time t8 is about twice an external access time t7 in a case where the read operation is given priority (FIG. 2). The increase in external access time is a big factor standing in the way of improving the device speed.